PAS5101CS Specification

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission

.

12

PixArt Imaging Inc.

v1.0 2005/4/27

slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits

DATA was also placed on SDA line by PAS5101CS. The 8 bits data was read from PAS5101CS internal

control register that address was assigned by previous write cycle. Follow the master acknowledgment,

the PAS5101CS place the next 8 bits data ( address is increment automatically ) on SDA line and then

transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte

read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS5101CS )

must releases SDA line to master to generate STOP condition.

4.3. I2C

4.4. I2C

Standard Mode

Parameter

Symbol

Min.

Max

Unit

SCL clock frequency.

10

400

KHz

Hold time ( repeated ) Start condition.

After this period, the first clock pulse is generated.

4.0

-

μ

s

Low period of the SCL clock.

4.7

-

μ

s

High period of the SCL clock.

0.75

-

μ

s

Set-up time for a repeated START condition.

4.7

-

μ

s