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TPS92002 数据表(PDF) 3 Page - Texas Instruments |
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TPS92002 数据表(HTML) 3 Page - Texas Instruments |
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3 / 14 page ![]() TPS92001, TPS92002 www.ti.com SLUSA24 – FEBRUARY 2010 ELECTRICAL CHARACTERISTICS VVDD = 12 V, CREF = 0.47-mF, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION VDD Supply clamp IVDD = 10 mA 16 17.5 19 V IVDD Supply current No Load 600 900 µA IVDD Supply current startup(1) 110 µA TPS92001 110 125 Supply current standby VVDD = Start threshold – 300 mv µA TPS92002 130 170 UNDERVOLTAGE LOCKOUT SECTION TPS92001 9.4 10.4 Start threshold TPS92002 14.0 15.6 V TPS92001 1.65 UVLO hysteresis TPS92002 6.2 VOLTAGE REFERENCE SECTION Output voltage IREF = 0 mA 4.75 5 5.25 V Line regulation 10 V ≤ VVDD ≤ 15 V 2 mV Load regulation 0 mA ≤ IREF ≤ 5 mA 2 mV COMPARATOR SECTION ICS Current sense Output OFF -100 nA Comparator threshold 0.9 0.95 1 V GDDLY GD propagation delay (No Load) 0.8 V ≤ VCS ≤ 1.2 V at TR = 10 ns 50 100 ns SOFT START SECTION VVDD = 16 V, VSS = 0 V, -40°C ≤ TA ≤ 85°C -4.9 -7.0 -9.1 µA ISS Soft-start current VVDD = 16 V, VSS = 0 V, -40°C ≤ TA ≤ 85° -4.9 -7.0 -10.0 µA VSS Low-level output voltage VVDD = 7.5 V, ISS = 200 µA 0.2 V Shutdown threshold 0.44 0.48 0.52 V OSCILLATOR SECTION RRTC = 10 kΩ, RRTD = 4.32 kΩ, CCT = Switching frequency 90 100 110 kHz 820pF Frequency change with voltage 10 V ≤ VVDD ≤ 15 V 0.1 %/V VCT(peak) Timing capacitor peak voltage 3.33 V VCT(valley) Timing capacitor valley voltage 1.67 V VCT(p-p) Timing capacitor peak-to-peak voltage 1.54 1.67 1.80 V GATE DRIVE SECTION Power driver VSAT low IGD = 80 mA (dc) 0.8 1.5 V Power driver VSAT high IGD = -40 mA (dc), (VVDD – VGD) 0.8 1.5 V Power driver low-voltage during UVLO IGD = 20 mA (dc) 1.5 V DMIN Minimum duty cycle VCS = 2 V 0% DMAX Maximum duty cycle 70% tRISE Rise Time CGD = 1nF 35 ns tFALL Fall Time CGD = 1nF 18 ns (1) Specified by design. Not production tested. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPS92001 TPS92002 |
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