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ADRF6603ACPZ-R7 数据表(PDF) 17 Page - Analog Devices

部件名 ADRF6603ACPZ-R7
功能描述  2100 MHz to 2600 MHz Rx Mixer with Integrated Fractional-N PLL and VCO
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6603ACPZ-R7 数据表(HTML) 17 Page - Analog Devices

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ADRF6603
Rev. 0 | Page 17 of 24
APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
Figure 21 shows the schematic for the ADRF6603 evaluation
board. The six power supply pins should be individually
decoupled using 100 pF and 0.1 μF capacitors located as
close as possible to the device. In addition, the internal decou-
pling nodes (DECL3P3, DECL2P5, and DECLVCO) should
be decoupled with the capacitor values shown in Figure 21.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor
is required from these outputs to VCC.
A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms
for a sine wave input) results in an IF output power of 4.7 dBm.
The reference frequency for the PLL should be from 12 MHz
to 160 MHz and should be applied to the REF_IN pin, which
should be ac-coupled and terminated with a 50 Ω resistor as
shown in Figure 21. The reference signal, or a divided-down
version of the reference signal, can be brought back off chip at
the multiplexer output pin (MUXOUT). A lock detect signal
and a voltage proportional to the ambient temperature can also
be selected on the multiplexer output pin.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see the
Evaluation Board Configuration Options section.
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
R22
0
Ω
(0402)
RFIN
MUX
RSET
CP
VTUNE
LODRV_EN
LON
LOP
2:1
MUX
VCO
CORE
TEMP
SENSOR
DECL2P5
DECL3P3
DECLVCO
BUFFER
BUFFER
IFN
IFP
2
14
5
3
IP3SET
RFIN
–
+
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
MUXOUT
REF_IN
ADRF6603
19
5
8
36
11
7
4
20
15
23
21
25
24
30
38
35
31
26
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG
MODULUS
INTEGER
REG
N COUNTER
21 TO 123
×2
÷2
÷4
DIVIDER
÷2
SPI
INTERFACE
C43
10µF
(0603)
C14
270pF
(0603)
CP
TEST
POINT
(ORANGE)
C13
27pF
(0603)
C40
OPEN
(0603)
C7
0.1µF
(0402)
VCC
RED
+5V
VCC
VTUNE
C15
5.6nF
(1206)
C2
OPEN
(0402)
C1
100pF
(0402)
R1
0
Ω
(0402)
R38
0
Ω
(0402)
R37
0
Ω
(0402)
R2
OPEN
(0402)
C42
10µF
(0603)
C17
0.1µF
(0402)
R63
OPEN
(0402)
R65 0
Ω
(0402)
R9 18k
Ω
(0402)
R12
0
Ω
(0402)
R10
1.6k
Ω
(0603)
R62
0
Ω
(0402)
R11
OPEN
(0402)
RFOUT
C16
100pF
(0402)
R18
0
Ω
(0402)
C41
OPEN
(0603)
C11
0.1µF
(0402)
C27
0.1µF
(0402)
C29
0.1µF
(0402)
C12
100pF
(0402)
R8
0
Ω
(0402)
R16
0
Ω
(0402)
C13
1nF
(0402)
C6
1nF
(0402)
R41
0
Ω
(0402)
R39
OPEN
(0402)
VCC1
RED
S1
OPEN
R40
0
Ω
(0402)
C5
1nF
(0402)
R73
49.9
Ω
(0402)
4
LO IN/OUT
REF_IN
REFOUT
3
51
T8
TC1-1-13+
R20
0
Ω
(0402)
R43
10k
Ω
(0402)
R19
0
Ω
(0402)
S2
R47
10k
Ω
(0402)
R35
0
Ω
(0402)
R30
0
Ω
(0402)
R42
OPEN
(0402)
R48
0
Ω
(0402)
R36
0
Ω
(0402)
P1
9-PIN
DSUB
VCC_LO
VCC2
VCC1
27
13
12
C8
100pF
(0402)
R6
0
Ω
(0402)
C27
0.1µF
(0402)
C26
100pF
(0402)
R27
0
Ω
(0402)
C25
0.1µF
(0402)
C24
100pF
(0402)
R26
0
Ω
(0402)
C23
0.1µF
(0402)
C22
100pF
(0402)
R25
0
Ω
(0402)
C20
0.1µF
(0402)
C21
100pF
(0402)
R24
0
Ω
(0402)
C19
0.1µF
(0402)
C18
100pF
(0402)
R17
0
Ω
(0402)
2
4
6
13
5
7
C30
OPEN
(0402)
R45
OPEN
(0402)
C32
OPEN
(0402)
R44
OPEN
(0402)
C31
OPEN
(0402)
14
DIV
BY
2, 1
VCC_MIX
VCC_V2I
VCC_LO
R27
0
Ω
(0402)
R43
0
Ω
(0402)
VCC
+5V
R27
0
Ω
(0402)
16
2
9
29
18
40
39
3
6
38
37
34
22
17
10
1
89
Figure 21. Basic Connections for Operation of the ADRF6603



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