ADRF6603

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

RF Specifications .......................................................................... 3

Synthesizer/PLL Specifications................................................... 4

Logic Input and Power Specifications ....................................... 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Register Structure ........................................................................... 11

Register 0—Integer Divide Control (Default: 0x0001C0)..... 11

Register 1—Modulus Divide Control (Default: 0x003001) .. 11

Register 2—Fractional Divide Control (Default: 0x001802) 12

Register 3—Σ-Δ Modulator Dither Control (Default:

0x10000B).................................................................................... 12

Register 4—PLL Charge Pump, PFD, and Reference Path

Control (Default: 0x0AA7E4)................................................... 13

Register 5—PLL Enable and LO Path Control (Default:

0x0000E5).................................................................................... 14

Register 6—VCO Control and VCO Enable (Default:

0x1E2106).................................................................................... 14

Register 7—Mixer Bias Enable and External VCO Enable

(Default: 0x000007).................................................................... 14

Theory of Operation ...................................................................... 15

Programming the ADRF6603................................................... 15

Initialization Sequence .............................................................. 15

LO Selection Logic ..................................................................... 16

Applications Information .............................................................. 17

Basic Connections for Operation............................................. 17

Evaluation Board ............................................................................ 18

Evaluation Board Control Software......................................... 18

Schematics and Artwork ........................................................... 20

Evaluation Board Configuration Options............................... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

3/10—Revision 0: Initial Version