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WM2148CFT/V 数据表(PDF) 6 Page - Wolfson Microelectronics plc

部件名 WM2148CFT/V
功能描述  14-bit 8MSPS Analogue-To-Digital Converter
PDF  14 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM2148CFT/V 数据表(HTML) 6 Page - Wolfson Microelectronics plc

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WM2148
Production Data
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
6
Digital Outputs
Output LOW level
VOL
IOUT = -50
µA0.4
V
Output HIGH level
VOH
IOUT = +50
µA2.6
V
High Impedance Output Current
IOZ
±10
µA
TERMINOLOGY
1.
DNL is the variation in the analogue step size associated with one digital output code across the input range,
normalised to full scale.
2.
INL is the maximum deviation of the analogue input voltage associated with a digital code from its ideal value,
normalised to full scale. Using the ‘best fit’ method, ideal values are taken from a straight line fitted to the ADC curve.
The INL figure thus obtained therefore characterises linearity only and is not affected by gain and offset errors.
3.
SNR is the ratio in dB of signal to noise amplitude when a full-scale sine wave is applied to the input.
4.
THD is the ratio in dB of the sum of all harmonics to signal amplitude when a full scale sine wave is applied to the
input.
5.
SFDR is the amplitude ratio the output signal to the largest spur (artifact) produced by the device.
t
d
ANALOGUE
INPUT
CLK
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
OUTPUT DATA
0
123456789
10
11
12
13
S13
S14
S15
14
15
16
S16
S0
S1
S2
S3
S4
S5
S6
Latency
Figure 1 Latency
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Clock Timing
Clock Frequency
fCLK
CS = Low
0.1
8
8
MHz
Output Delay Time
td
CS = Low
25
ns
Latency
CS = Low
9.5
cycles
OEB
CSB
D[0:13]
A[0:1]
DATA
XX
ADDRESS
t
su(OE-ACS)
t
dis
t
h(A)
t
en
t
h(CS)
Figure 2 Read Timing



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