Production Data

WM2148

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 February 2001

9

ADDRESS

A1

A0

REGISTER

0

0

0

ADC Conversion Result

1

0

1

PGA gain

2

1

0

DC Offset

3

1

1

Control

Table 2 WM2148 Internal Registers

The ADC data register contains the result of the last analogue to digital conversion. It can also be

used to reset the device to its default state by writing a ‘1’ to the LSB (D0). This will set all the bits in

the gain, offset and control registers to ‘0’. All other bits should always be set to zero when writing to

the ADC data register.

The PGA gain is controlled using the last three bits of Address 1. The eight possible binary values of

000 to 111 (decimal 7) correspond to a gain of 0 to 7dB, respectively.

The lower byte of Address 2 holds the offset value (in LSBs). This value is added to the ADC data if

the DCO bit in the Control register is set. The offset is in Two’s complement format, providing a

range of -128 to +127 LSB.

REG. / BIT

D13

D12

D11

D10

D9D8

D7D6D5D4

D3D2

D1D0

ADC Data

MSB

……

………

…………

……

…

LSB/

SR

PGA Gain

X

X

X

XXX

XXXX

X

G2

G1

G0

DC Offset

X

X

X

X

X

X

MSB

………

……

…

LSB

Control

PWD

REF

FOR

TM2

TM1

TM0

DCO

XXX

XX

XX

Table 3 WM2148 Register Map

The Control register (address 3) has four bits to program the device’s operation and three test mode

bits. Setting the Power Down bit (PWD) takes the device into Power Down mode. DCO enables the

addition of the offset value held at Address 2 to the ADC output data. REF selects between internal

and external reference voltages, and FOR between unsigned binary and Two’s complement output

format.

BIT

DESCRIPTION

0

1

PWD

Power Down

Normal Operation

Power Down

REF

Reference Select

Internal Reference

External Reference

FOR

Output Format

Unsigned Binary

Two’s Complement

DCO

DC Offset

Enable

Disable

SR

Software Reset

Normal Operation

Reset

X

Reserved

Always set to 0 when writing to any register.

Table 4 Control Bits and Software Reset

The ADC core can be tested by selecting one of six different test modes, which apply various

voltages to the analogue inputs. This may be useful for calibration purposes. The test modes are

controlled by the three test mode bits in the control register, TM0 to TM2 (see Table 5 below).

TM2

TM1

TM0

FUNCTION

0

0

0

Normal Operation

0

0

1

Both inputs = REF-

010

0

1

1

IN+ at REF+, IN- at REF-

1

0

0

Normal Operation

1

0

1

Both inputs = REF+

1

1

0

1

1

1

IN+ at REF-, IN- at REF+

Table 5 Test Modes