WM2331

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.4 April 2001

22

DRIVING REFTF AND REFBF (FULL EXTERNAL REFERENCE MODE)

680R

AVDD

AGND

AVDD

AGND

REFTF

REFBF

To REFBS

(for Kelvin

connection)

To REFTS

(for Kelvin

connection)

Figure 26 Equivalent Circuit of REFTF and REFBF Inputs

DESIGNING THE DC CLAMP

Figure 16 (in Device Description) shows the basic operation of the clamp circuit with the analog input

AIN coupled via an RC circuit. The clamp voltage output level may be established by an analog

voltage on the CLAMPIN pin or by programming the on-chip clamp DAC.

INITIAL CLAMP ACQUISITION TIME

Initial acquisition time is defined as the time required to reach the target clamp voltage at AIN when

the clamp switch SW1 is closed for the first time (clamp re-acquisition during normal operation is

discussed in Steady-state Clamp Voltage Error, below). This time is given by









×

×

=

E

C

IN

IN

ACQ

V

V

R

C

T

ln

time. The maximum tolerable error depends on the application requirements.

For example, consider clamping an incoming video signal that has a black level near 0.3V to a black

the source resistance Rin is 20

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duration required to reach this error is:

µF × 20Ω × ln(1/0.01) = 92µs (approx.)

Note that during continuous operation, the clamping time would typically be much shorter, as the

voltage difference wolud be smaller (depending on droop, see next section.

Initial acquisition can be performed in two ways:

•

Pulsing the CLAMP pin as in normal operation. Provided that clamp droop (see below)

is negligible, initial acquisition is complete when the total clamped (CLAMP = HIGH)

•

Pulling the CLAMP pin high for the required acquisition time before starting normal

operation. This method is faster.

CLAMP DROOP

The charging currents drawn by the Sample-and-Hold switched capacitor input can charge or

during the time between clamp pulses. This effect is called clamp droop.