Production Data

WM2331

WOLFSON MICROELECTRONICS LTD

PD Rev 1.4 April 2001

23

D

IN

IN

DROOP

t

C

I

V

×









≈

(approx.)

Worst case droop between clamping intervals occurs for maximum input bias current. Maximum

µA for a 2V input range at AIN (see ‘Driving the

±

30% because of processing variations and voltage dependencies. Designs should allow for this

level droop between clamp pulses is

µ6Ãà AÃ×Ã%"$ †Ã2Ã!$€WÃhƒƒ…‚‘

= 1.25LSB at PGA gain=1, 2V ADC references

and hence reduce the voltage change between clamp pulses.

If a high leakage capacitor is used for coupling the input source to the AIN pin then the droop may be

significantly worse than calculated above. Avoid using electrolytic and tantalum coupling capacitors

as these have higher leakage currents than non-polarised capacitor types. Electrolytic and tantalum

capacitors also tend to have higher parasitic inductance, which can cause problems at high input

frequencies.

STEADY-STATE CLAMP VOLTAGE ERROR

During the clamp pulse (CLAMP = HIGH), the DC voltage on AIN is refreshed from the clamp

voltage. Provided that droop is not excessive, clamping fully reverses the effect of droop. However,

Figure 27 shows the approximate voltage waveform at AIN resulting from a a large clamp droop

Vclamp

VM

V

tc

td

V

DROOP

=

V

AIN

∆

AIN

V

COS

Figure 27 Approximate Waveforms at AIN During Droop and Clamping

The voltage change at AIN during acquisition has been approximated as a linear charging ramp by

during clamp acquisition is then

IN

IN

D

COS

AIN

C

R

t

V

V

×

×

=

∆

The peak-to-peak voltage variation at AIN must equal the clamp droop voltage at steady state.

Equating the droop voltage to the clamp acquisition voltage change gives

C

D

IN

IN

COS

t

t

I

R

V

×

×

=

unreasonably large.