WM2604

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 June 1999

6

SERIAL INTERFACE

NCS

FS

SCLK

DIN

1

2

3

4

5 15

16

D0

D1

D12

D13

D14

D15

t

WL

t

WH

t

SUD

t

HD

t

SUCSFS

t

SUC16CS

t

WHFS

t

SUFSCLK

t

SUC16FS

Figure 1 Timing Diagram

Test Conditions:

Ω, C

recommended operating free-air temperature range (unless noted otherwise)

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Setup time NCS low before negative FS edge.

10

ns

Setup time FS low before first negative SCLK edge.

8

ns

Setup time, sixteenth negative SCLK edge after FS low

on which D0 is sampled before rising edge of FS.

10

ns

Setup time, sixteenth positive SCLK edge (first positive

after D0 sampled) before NCS rising edge.

If FS is used instead of the sixteenth positive edge to

update the DAC, then the setup time is between the FS

rising edge and the NCS rising edge.

10

ns

Pulse duration, SCLK high.

25

ns

Pulse duration, SCLK low.

25

ns

Setup time, data ready before SCLK falling edge.

8

ns

Hold time, data held valid after SCLK falling edge.

5

ns

Pulse duration, FS high.

20

ns