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WM2616CD 数据表(PDF) 5 Page - Wolfson Microelectronics plc |
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WM2616CD 数据表(HTML) 5 Page - Wolfson Microelectronics plc |
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5 / 9 page ![]() Production Data Rev 1.0 WM2616 WOLFSON MICROELECTRONICS LTD Production Data Rev 1.0 June 1999 5 SERIAL INTERFACE t SUC16FS t SUFS SCLK DIN NCS FS 1 2 3 4 5 15 16 D0 D1 D12 D13 D14 D15 t WL t WH t SUD t HD t SUCSFS t WHFS t SUC16CS Figure 1 Timing Diagram Test Conditions: RL = 10k Ω, C L = 100pF. VDD = 5V ±± 10%, V REF = 2.048V and VDD = 3V ±± 10%, V REF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tSUCSFS Setup time NCS low before negative FS edge. 10 ns tSUFS Setup time FS low before first negative SCLK edge. 8 ns tSUC16FS Setup time, sixteenth negative SCLK edge after FS low on which D0 is sampled before rising edge of FS. 10 ns tSUC16CS Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and the NCS rising edge. 10 ns tWH Pulse duration, SCLK high. 25 ns tWL Pulse duration, SCLK low. 25 ns tSUD Setup time, data ready before SCLK falling edge. 8 ns tHD Hold time, data held valid after SCLK falling edge. 5 ns tWHFS Pulse duration, FS high. 20 ns |
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