WM2633CDT datasheet(6/12 Pages) WOLFSON

6 / 12 page

WM2633

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V

supply current will increase.

9. Typical supply current in powerdown mode is 10nA. Production test limits are wider for speed of test.

10. Slew rate results are for the lower value of the rising and falling edge slew rates.

11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and

falling edges. Limits are ensured by design and characterisation, but are not production tested.

12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with

a sampling frequency fS .

PARALLEL INTERFACE

D[0-7]

A[0-1]

NCS

NWE

NLDAC

Data

Address

SUD

SUA

SUCSWE

WWE

SUWELD

WLD

Figure 1 Timing Diagram

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

tSUCSWE

Setup time NCS low before positive NWE edge

tSUD

Data ready before positive NWE edge

tHD

Data hold after positive NWE edge

5ns

tSUA

Setup time for address bits A0, A1

tSUWELD

Positive NWE edge before NLDAC low

5ns

tWWE

High pulse width of NWE

tWLD

Low pulse width of NLDAC

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