Wolfson Microelectronics

10

WM5620L, WM5620

Functional Description

DAC operation

Each of WM5620/L 's four digital to analogue converters

(DACs) are implemented using a single resistor string with

256 taps corresponding to each of the input 8-bit codes.

One end of a resistor string is connected to the GND pin

and the other end is driven from the output of a reference

input buffer. The use of a resistor string guarantees

monotonicity of the DAC's output voltage. Linearity depends

upon the matching of the resistor string's individual elements

and the performance of the output buffer. The reference input

buffers present a high impedance to reference sources.

Each DAC has a voltage output amplifier which is

programmable for gains of x1 or x 2 through the serial

interface. The DAC output amplifiers feature rail to rail

output stages, allowing outputs over the full supply voltage

range to be achieved with a x 2 gain setting and a VDD/2

reference voltage input. Used in this way a slight

degradation in linearity will occur as the output voltage

approaches VDD.

A power-on-reset activates at power up resetting the DACs

inputs to code 0. Each output voltage is given by:

Where:

RNG controls the output gains of x 1 and x 2

CODE is the range 0 to 255

Pin Descriptions

Pin

Name

Type

Function

1

GND

Supply

Ground return and reference terminal

2

RefA

Analogue input

Reference voltage input to DACA

3

RefB

Analogue input

Reference voltage input to DACB

4

RefC

Analogue input

Reference voltage input to DACC

5

RefD

Analogue input

Reference voltage input to DACD

6

Data

Digital input

Serial interface data

7

Clk

Digital input

Serial interface clock, negative edge sensitive

8

Load

Digital input

Serial interface load

9

DACD

Analogue output

DAC D output

10

DACC

Analogue output

DAC C output

11

DACB

Analogue output

DAC B output

12

DACA

Analogue output

DAC A output

13

LDAC

Digital input

DAC update latch control

14

Supply

positive supply voltage

Data Interface

WM5620/L's four double buffered DAC inputs allow

several ways of controlling the update of each DAC's

output.

Serial data is input, MSB first, into the DATA input pin using

CLK, LOAD and LDAC control inputs and comprises 2 DAC

address bits, an output range (RNG) bit and 8 DAC input

bits.

With the LOAD pin high data is clocked into the DATA pin

on each falling edge of CLK. Any number of data bits may

be clocked in, only the last 11 bits are used. When all data

bits have been clocked in, a falling edge at the LOAD pin

latches the data and RNG bits into the correct 9 bit input

latch using the 2 bit DAC address.

If the LDAC input pin is low, the second latch at the DAC

input is transparent, and the DAC input and RNG bit will be

updated on the falling edge of LOAD simultaneously with

the input latch, as shown in figure 1. If the LDAC input is high

during serial data input, as shown in figure 2, the falling edge

of the LOAD input stores the data in the addressed input

latch. The falling edge of LDAC updates the second latches

from the input latches and hence the DAC outputs.