Production Data

WM9704M

WOLFSON MICROELECTRONICS LTD

PD Rev 3.2 January 2001

31

Bits 7 to 0 are read only, 1 indicates modem AFE subsystem readiness. Bits 15 to 8 are read/write

and control modem AFE subsystem power-down. Writing ENABLES (0) to the above aliased PR bits

is allowed and will write enable to appropriate PRN bit. However, writing DISABLES (1) is not

allowed.

REGISTER 40H – LINE1 ADC/DAC SAMPLE RATE

This read/write register 40h controls the modem DAC and ADC sample rate. This register is only

functional if Modem mode 1 = 1 is selected from pins 30 and 40. The ADC will only use this sample

rate if in addition, the input to the Record Mux is selected, as Right ADC is PHONE in register 1Ah.

Note only the recommended sample rates are supported. If alternative sample rates are selected the

rate will default to the nearest sample rate supported, and that value will be read back.

REGISTER 46H TO 48H – LINE1 AND 2 DAC/ADC LEVEL

These registers are not supported in WM9704M, register 04h being used to control TX modem level.

REGISTER 56H – MISCELLANEOUS MODEM AFE STATUS/CONTROL

This read/write register defines the loop back modes available for the modem line and handset

ADCs/DACs described in the Intel Specification. Line1 ADC loopback mode 001 L1B0 is supported.

GPIO FUNCTION

Note that only the three GPIO pins are supported, GPIO 11 to 13.

REGISTER 4CH – GPIO PIN CONFIGURATION REGISTER

The GPIO Pin Configuration is a read/write register that specifies whether a GPIO pin is configured

for input (1) or for output (0), and is accessed via the standard slot 1 and 2 command address/data

protocols.

If a GPIO pin is implemented, the respective GCx bit should be read/writeable and set to 1. If a GPIO

is not implemented, then the respective GCx bit is read-only and set to 0. This informs the software

how many GPIO pins have been implemented. It is up to the AC’97 Digital Controller to send the

desired GPIO pin value over output slot 12 in the outgoing stream of the AC-link before configuring

any of these bits for output. The default value after cold or register reset for this register (3800h) is all

pins configured as inputs.

REGISTER 4EH – GPIO PINS POLARITY/TYPE

The GPIO Pin Polarity/Type is a read/write register that defines GPIO Input Polarity (0 = Low,

1 = High active) when a GPIO pin is configured as an Input. It defines GPIO Output Type

(1 = CMOS, 0 = OPEN-DRAIN) when a GPIO pin is configured as an Output.

The default value after cold or register reset for this register (FFFFh) is all pins active high.

Non-implemented GPIO pins always return 1s.

REGISTER 50H – GPIO PIN STICKY CONTROL

The GPIO Pin Sticky is a read/write register that defines GPIO Input Type (0 = Non-sticky,

1 = Sticky) when a GPIO pin is configured as an input. GPIO inputs configured as sticky are cleared

by writing a 0 to the corresponding bit of the GPIO pin status register 54h (see below), and by reset.

The default value after cold or register reset for this register (0000h) is all pins Non-sticky.

Unimplemented GPIO pins always return 0s. Sticky is defined as edge-sensitive, Non-sticky as level

sensitive.

REGISTER 52H – GPIO PIN WAKE-UP CONTROL

The GPIO Pin Wake-up is a read/write register that provides a mask for determining if an input GPIO

change will generate a wake-up or GPIO_INT (0 = No, 1 = Yes). When the AC-Link is powered down

(Register 26h PR4 = 1 for primary codecs), a wake-up event will trigger the assertion of SDATA_IN.

When AC-link is powered up, a wake-up event will appear as GPIO_INT = 1 on bit 0 of input slot 12.

GPIO_INT is also flagged when the link is active.

An AC-link wake-up Interrupt is defined as a 0 to 1 transition on SDATA_IN when the AC-Link is

powered down (Register 26h PR4 = 1). GPIO bits that have been programmed as inputs, sticky and

pin wake-up, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause

an AC-link wake-up event (transition of SDATA_IN from 0 to 1), if and only if the AC-link was

powered down.