WM9704M

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.2 January 2001

32

The default value after cold or register reset for this register (0000h) defaults to all 0s specifying no

wake-up event. Non-implemented GPIO pins always return 0s.

REGISTER 54H – GPIO PIN STATUS

The GPIO status is a read/write register that reflects the state of all GPIO pins (inputs and outputs)

on slot 12. The value of all GPIO pin inputs and outputs comes in from the codec every frame on slot

12, but is also available for reading as GPIO Pin Status via the standard slot 1 and 2 command

address/data protocols. GPIO inputs configured as Sticky are cleared by writing a 0 to the

corresponding bit of this register 54h.

Bits corresponding to unimplemented GPIO pins should be forced to zero in this register and input

slot 12. GPIO bits that have been programmed as Inputs and Sticky, upon transition either (high-to

low) or (low-to-high) depending on pin polarity, will cause the individual GPIO bit to go asserted 1,

and remain asserted until a write of 0 to that bit. The normal way to set the desired value of a GPIO

output pin is to set the control bit in output slot 12.

The default value, if configured as an input, after cold or register reset for this register is always the

state of the GPIO pin.

REGISTER 56H – MISCELLANEOUS MODEM AFE STATUS/CONTROL

This read/write register defines the loopback modes available for the modem line and handset

ADCs/DACs described in the Intel Specification. Line1 ADC loopback mode 001 L1B0 is supported.

VENDOR RESERVED REGISTERS (INDEX 5AH AND 7AH)

These registers are vendor specific. Do not write to these registers unless the Vendor ID register has

been checked first to ensure that the driver knows the source of the AC‘97 component. Values stored

in this register are used to provide vendor specific modes for the manufacturer.

BIT

NAME

DEFAULT

ACTION WHEN SET TO 1

Test only bits – not normal use

AEV

ADC evaluation

0

ADC evaluation mode select bit – do not use

BB

BIASBOOST

0

Increases analogue bias currents by 50%

TRM

TSTRECMUX

0

Enables record mux test mode; RECMUX outputs

summed into the front and rear DAC output path.

HIC

HALFICONV

0

Halves to bias current to the converters

HIM

MALFIMIX

0

Halves bias current to the mixer block

DDS

Dither disable

0

Disables ADC and DAC digital dither – do not use

RTS

RAM test mode

0

Digital test mode – do not use

DFT

DAC FIT test

0

Digital test mode – do not use

AFT

ADC FIR test

0

Digital test mode – do not use

DTS

DAC test

0

Digital test mode – do not use

ATS

ADC test

0

Digital test mode – do not use

User bits

AND

ADC no DAC

0

Select stereo mix into ADC as having no DAC

signal

R2S

Rev 2.1 switch

0

Closes Rev 2.1 switch when set (see fig 1)

I

I

0

Enables I

43,44,48

DLM

Dual line modem

0

Selects support for Line2 DAC and ADC slots

ADS

Automute disable

0

Disables automute function on the front and rear

DACs

Table 20 Vendor Register 5Ah Bit Allocation and Default States

Vendor specific Gain control registers – (Index 70h to 74h). The function is as per the other mixer

PGAs. However, the default value of the register changes depending upon the MODE the device is

operating in, as shown in Table 21.