数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

X24C01API-3 数据表(PDF) 4 Page - Xicor Inc.

部件名 X24C01API-3
功能描述  Serial E2PROM
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  XICOR [Xicor Inc.]
网页  http://www.xicor.com
标志 XICOR - Xicor Inc.

X24C01API-3 数据表(HTML) 4 Page - Xicor Inc.

  X24C01API-3 Datasheet HTML 1Page - Xicor Inc. X24C01API-3 Datasheet HTML 2Page - Xicor Inc. X24C01API-3 Datasheet HTML 3Page - Xicor Inc. X24C01API-3 Datasheet HTML 4Page - Xicor Inc. X24C01API-3 Datasheet HTML 5Page - Xicor Inc. X24C01API-3 Datasheet HTML 6Page - Xicor Inc. X24C01API-3 Datasheet HTML 7Page - Xicor Inc. X24C01API-3 Datasheet HTML 8Page - Xicor Inc. X24C01API-3 Datasheet HTML 9Page - Xicor Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 13 page
background image
X24C01A
4
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C01A this is fixed as
1010[B].
Following the start condition, the X24C01A monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A0,
A1 and A2 inputs). Upon a correct compare the X24C01A
outputs an acknowledge on the SDA line. Depending on
the state of the R/
W bit, the X24C01A will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C01A requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 128 words of memory. Note: the most significant bit
is a don’t care. Upon receipt of the word address the
X24C01A responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24C01A
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C01A
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
Figure 4. Slave Address
The next three significant bits address a particular
device. A system could have up to eight X24C01A
devices on the bus (see Figure 10). The eight addresses
are defined by the state of the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
Figure 6. Page Write
1
0
1
0
A2
A1
A0
R/W
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
3841 FHD F08
3841 FHD F09
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
3841 FHD F10
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com