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ADP1650ACBZ-R7 数据表(PDF) 5 Page - Analog Devices |
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ADP1650ACBZ-R7 数据表(HTML) 5 Page - Analog Devices |
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5 / 32 page  ADP1650 Rev. 0 | Page 5 of 32 I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3. Parameter1 Min Max Unit Description fSCL 400 kHz SCL clock frequency tHIGH 0.6 µs SCL high time tLOW 1.3 µs SCL low time tSU, DAT 100 ns Data setup time tHD, DAT 0 0.9 µs Data hold time tSU, STA 0.6 µs Setup time for repeated start tHD, STA 0.6 µs Hold time for start/repeated start tBUF 1.3 µs Bus free time between a stop and a start condition tSU, STO 0.6 µs Setup time for stop condition tR 20 + 0.1 CB2 300 ns Rise time of SCL and SDA tF 20 + 0.1 CB2 300 ns Fall time of SCL and SDA tSP 0 50 ns Pulse width of suppressed spike CB2 400 pF Capacitive load for each bus line 1 Guaranteed by design. 2 CB is the total capacitance of one bus line in picofarads. SDA SCL S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Sr P S tLOW tR tHD, DAT tHIGH tSU, DAT tF tF tSU, STA tHD, STA tSP tSU, STO tBUF tR Figure 3. I2C-Compatible Interface Timing Diagram |
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