750 MHz to 1160 MHz Rx Mixer with

Integrated Fractional-N PLL and VCO

ADRF6601

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthird

license is grant

Trademarksand

9106, U.S.A.

analog.com

s reserved.

partiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

ed by implication or otherwise under any patent or patent rights of Analog Devices.

registeredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-

Tel: 781.329.4700

www.

Fax: 781.461.3113

©2010 Analog Devices, Inc. All right

FEATURES

Rx mixer with integrated fractional-N PLL

RF input frequency range: 300 MHz to 2500 MHz

Internal LO frequency range: 750 MHz to 1160 MHz

Input P1dB: 14.2 dBm

Input IP3: 30.0 dBm

IIP3 optimization via external pin

SSB noise figure

IP3SET pin open: 13.0 dB

IP3SET pin at 3.3 V: 13.8 dB

Voltage conversion gain: 6.7 dB

Matched 200 Ω IF output impedance

IF 3 dB bandwidth: 500 MHz

Programmable via 3-wire SPI interface

40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Cellular base stations

GENERAL DESCRIPTION

The ADRF6601 is a high dynamic range active mixer with an

integrated fractional-N phase-locked loop (PLL) and a voltage-

controlled oscillator (VCO) for internal mixer LO generation.

Along with the ADRF6602 and the ADRF6603, the ADRF6601

forms a family of integrated PLL/mixers. The ADRF6601 covers

the frequency range of 750 MHz to 1160 MHz.

The PLL reference input can support input frequencies from

12 MHz to 160 MHz. The PFD output controls a charge pump

whose output drives an off-chip loop filter.

The loop filter output is then applied to an integrated VCO. The

programmable PLL divider. The programmable PLL divider is

controlled by a Σ-Δ modulator (SDM). The modulus of the SDM

can be programmed from 1 to 2047.

The active mixer converts the single-ended 50 Ω RF input to

a 200 Ω differential IF output. The IF output can operate up

to 500 MHz.

The ADRF6601 is fabricated using an advanced silicon-germanium

BiCMOS process. It is available in a 40-lead, RoHS-compliant,

6 mm × 6 mm LFCSP with an exposed paddle. Performance is

specified over the −40°C to +85°C temperature range.

Table 1.

Part No.

Internal

LO Range

±3 dB RF Input

Balun Range

±1 dB RF Input

Balun Range

ADRF6601

750 MHz to

1160 MHz

300 MHz to

2500 MHz

450 MHz to

1600 MHz

ADRF6602

1550 MHz to

2150 MHz

1000 MHz to

3100 MHz

1350 MHz to

2750 MHz

ADRF6603

2100 MHz to

2600 MHz

1100 MHz to

3200 MHz

1450 MHz to

2850 MHz

FUNCTIONAL BLOCK DIAGRAM

VCC1

VCC2

VCC_LO

VCC_MIX

VCC_V2I

VCC_LO

NC NC

32

33

1

10

17

22

27

34

MUX

CP VTUNE

LODRV_EN

LON

LOP

IP3SET

2:1

MUX

VCO

CORE

TEMP

SENSOR

DECLVCO

DECL2P5

DECL3P3

IFP

BUFFER

BUFFER

IFN

–

+

CHARGE PUMP

250µA,

500µA (DEFAULT),

750µA,

1000µA

PRESCALER

÷2

LE

CLK

SPI

INTERFACE

DATA

MUXOUT

3.3V

LDO

2.5V

LDO

VCO

LDO

ADRF6601

INTERNAL LO RANGE

750MHz TO 1160MHz

36

DIV

BY

4, 2, 1

2

37

9

38

PLL_EN

REF_IN

GND

19

18

39

3

5

4

8

6

14

13

12

16

7 11 15 20 21 23 24 25 28 30 31 35

40

FRACTION

REG

MODULUS INTEGER

REG

26

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

29

PHASE

FREQUENCY

DETECTOR

N COUNTER

21 TO 123

×2

÷2

÷4

Figure 1.