HAL 710, HAL 730

DATA SHEET

6

Oct. 13, 2009; DSH000031_002EN

Micronas

2. Functional Description

The HAL 710 and the HAL 730 are monolithic inte-

grated circuits with two independent subblocks each

consisting of a Hall plate and the corresponding com-

parator. Each subblock independently switches the

comparator output in response to the magnetic field at

the location of the corresponding sensitive area. If a

magnetic field with flux lines perpendicular to the sen-

sitive area is present, the biased Hall plate generates a

Hall voltage proportional to this field. The Hall voltage

is compared with the actual threshold level in the com-

parator.

The output of comparator 1 (connected to S1) directly

controls the Count Output. The outputs of both com-

parators enter the Direction Detection Block controlling

the state of the Direction Output. The Direction Output

is updated at every edge of comparator 1 (rising and

falling). The previous state of the Direction Output is

maintained between two edges of the Count Output

and

in

case

the

edges

at

comparator 1

and

comparator 2 occur in the same clock period. The sub-

blocks are designed to have closely matched switching

points.

The temperature-dependent bias – common to both

subblocks – increases the supply voltage of the Hall

plates and adjusts the switching points to the decreas-

ing induction of magnets at higher temperatures. If the

magnetic field exceeds the threshold levels, the com-

parator switches to the appropriate state. The built-in

hysteresis prevents oscillations of the outputs.

In order to achieve good matching of the switching

points of both subblocks, the magnetic offset caused

by mechanical stress is compensated for by use of

switching offset compensation techniques. Therefore,

an internal oscillator provides a two-phase clock to

both subblocks. For each subblock, the Hall voltage is

sampled at the end of the first phase. At the end of the

second phase, both sampled and actual Hall voltages

are averaged and compared with the actual switching

point.

Shunt protection devices clamp voltage peaks at the

an internal series resistor up to

−15 V. No external

reverse voltages ranging from 0 V to

−15 V.

Fig. 2–1: HAL 710 timing diagram with respect to the

clock phase

Fig. 2–2 and Fig. 2–3 on page 7 show how the output

signals are generated by the HAL 710 and the

HAL 730. The magnetic flux density at the locations of

the two Hall plates is shown by the two sinusodial

curves at the top of each diagram. The magnetic

switching points are depicted as dashed lines for each

Hall plate separately.

At the time t = 0, the signal S2 precedes the signal S1.

The Direction Output is in the correct state according

to the definition of the sensor type.

When the phase of the magnetic signal changes its

sign, the Direction-Output switches its state with the

next signal edge of the Count Output.

t

Direction

t

Count

t

t

Clock

t

Output

Output