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AM1808AZCED3 数据表(PDF) 222 Page - Texas Instruments

部件名 AM1808AZCED3
功能描述  AM1808 ARM Microprocessor
PDF  264 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM1808AZCED3 数据表(HTML) 222 Page - Texas Instruments

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AM1808
SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010
www.ti.com
6.26.2 uPP Electrical Data/Timing
Table 6-116. Timing Requirements for uPP (see Figure 6-69, Figure 6-70, Figure 6-71, Figure 6-72)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
SDR mode
13.33
20
26.66
ns
1
tc(INCLK)
Cycle time, CHn_CLK
DDR mode
26.66
40
53.33
SDR mode
5
8
10
ns
2
tw(INCLKH)
Pulse width, CHn_CLK high
DDR mode
10
16
20
SDR mode
5
8
10
ns
3
tw(INCLKL)
Pulse width, CHn_CLK low
DDR mode
10
16
20
4
tsu(STV-INCLKH)
Setup time, CHn_START valid before CHn_CLK high
4
5.5
6.5
ns
5
th(INCLKH-STV)
Hold time, CHn_START valid after CHn_CLK high
0.8
0.8
0.8
ns
6
tsu(ENV-INCLKH)
Setup time, CHn_ENABLE valid before CHn_CLK high
4
5.5
6.5
ns
7
th(INCLKH-ENV)
Hold time, CHn_ENABLE valid after CHn_CLK high
0.8
0.8
0.8
ns
Setup time, CHn_DATA/XDATA valid before CHn_CLK
8
tsu(DV-INCLKH)
4
5.5
6.5
ns
high
9
th(INCLKH-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
0.8
0.8
0.8
ns
10
tsu(DV-INCLKL)
Setup time, CHn_DATA/XDATA valid before CHn_CLK low
4
5.5
6.5
ns
11
th(INCLKL-DV)
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
0.8
0.8
0.8
ns
19
tsu(WTV-INCLKL)
Setup time, CHn_WAIT valid before CHn_CLK high
10
12
14
ns
20
th(INCLKL-WTV)
Hold time, CHn_WAIT valid after CHn_CLK high
0.8
0.8
0.8
ns
21
tc(2xTXCLK)
Cycle time, 2xTXCLK input clock(1)
6.66
10
13.33
ns
(1)
2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-117. Switching Characteristics Over Recommended Operating Conditions for uPP
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
SDR mode
13.33
20
26.66
ns
12
tc(OUTCLK)
Cycle time, CHn_CLK
DDR mode
26.66
40
53.33
SDR mode
5
8
10
ns
13
tw(OUTCLKH)
Pulse width, CHn_CLK high
DDR mode
10
16
20
SDR mode
5
8
10
ns
14
tw(OUTCLKL)
Pulse width, CHn_CLK low
DDR mode
10
16
20
15
td(OUTCLKH-STV)
Delay time, CHn_START valid after CHn_CLK high
2
11
2
15
2
21
ns
16
td(OUTCLKH-ENV)
Delay time, CHn_ENABLE valid after CHn_CLK high
2
11
2
15
2
21
ns
17
td(OUTCLKH-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK high
2
11
2
15
2
21
ns
18
td(OUTCLKL-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK low
2
11
2
15
2
21
ns
222
Peripheral Information and Electrical Specifications
Copyright © 2010, Texas Instruments Incorporated
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