74LVC595A_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 29 May 2007

5 of 19

NXP Semiconductors

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

7.

Functional description

[1]

H = HIGH voltage state;

L = LOW voltage state;

↑ = LOW-to-HIGH transition;

X = don’t care;

NC = no change;

Z = high-impedance OFF-state.

8.

Limiting values

[1]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2]

For SO16 packages: above 70

For TSSOP16 packages: above 60

For DHVQFN16 packages: above 60

Table 3.

Function table[1]

Input

Output

Function

SHCP STCP OE

MR

DS

Q7S

Qn

X

X

L

L

X

L

NC

a LOW-state on MR only affects the shift register

X

↑

L

L

X

L

L

empty shift register loaded into storage register

X

X

H

L

X

L

Z

shift register clear; parallel outputs in high impedance OFF-state

↑

X

L

H

H

Q6S

NC

logic HIGH-state shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X

↑

L

H

X

NC

QnS

contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

↑↑

L

H

X

Q6S

QnS

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.5

+6.5

V

input clamping current

−50

-

mA

input voltage

[1]

−0.5

+6.5

V

output clamping current

-

±50

mA

output voltage

3-state

[1]

−0.5

6.5

V

output HIGH or LOW state

[1]

−0.5

V

output current

-

±50

mA

supply current

-

100

mA

ground current

−100

-

mA

storage temperature

−65

+150

°C

total power dissipation

[2] -

500

mW