EP7311 datasheet(39/58 Pages) CIRRUS

39 / 58 page

DS506F1

©Copyright Cirrus Logic, Inc. 2005

EP7311

High-Performance, Low-Power System on Chip

C20

nPOR

Schmitt

Power-on reset input

PB[7]

Input

‡

GPIO port B

RXD[2]

UART 2 receive data

input

VDDIO

Pad power

Digital I/O power,

3.3V

D18

VSSIO

Pad ground

I/O ground

D19

nBATCHG

Battery changed

sense input

D20

A[7]

Low

System byte address

PB[4]

Input

‡

GPIO port B

TXD[2]

High

UART 2 transmit

data output

WRITE/nSDRAS

Low

Transfer direction /

SDRAM RAS signal

output

E18

nMEDCHG/nBROM

Media change

interrupt input /

internal ROM boot

enable

E19

nEXTPWR

External power

supply sense input

E20

D[9]

Low

I/O

Data I/O

PB[3]

Input

‡

I/O

GPIO port B

PB[6]

Input

‡

I/O

GPIO port B

TDI

with p/u*

JTAG data input

F18

D[7]

Low

I/O

Data I/O

F19

A[8]

Low

System byte address

F20

D[10]

Low

I/O

Data I/O

PB[1]

Input

‡

I/O

PB[2]

Input

‡

I/O

GPIO port B

PB[5]

Input

‡

I/O

GPIO port B

G18

D[8]

Input

‡

I/O

Data I/O

G19

A[9]

Low

System byte address

G20

D[11]

Low

I/O

Data I/O

PA[7]

Input

‡

I/O

GPIO port A

H[2]

TDO

Input

‡

JTAG data out

H[3]

PB[0]

Input

‡

I/O

GPIO port B

H[18]

A[10]

Low

System byte address

Table 21. 204-Ball TFBGA Ball Listing (Continued)

Ball Location

Name

Strength

†

Reset

State

Type

Description

EP7311 数据表(PDF) 39 Page - Cirrus Logic

EP7311 数据表(HTML) 39 Page - Cirrus Logic

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EP7311 数据表(PDF) 39 Page - Cirrus Logic

EP7311 数据表(HTML) 39 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

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