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TMS320C6726BRFP300 数据表(PDF) 49 Page - Texas Instruments |
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TMS320C6726BRFP300 数据表(HTML) 49 Page - Texas Instruments |
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49 / 118 page  4.11.3 EMIF Electrical Data/Timing TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point Digital Signal Processors www.ti.com SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008 Table 4-5 through Table 4-10 assume testing over recommended operating conditions (see Figure 4-7 through Figure 4-13). Table 4-5. 100-MHz EMIF SDRAM Interface Timing Requirements(1) NO. MIN MAX UNIT 19 tsu(EM_DV-EM_CLKH) Input setup time, read data valid on D[31:0] before EM_CLK rising 3 ns 20 th(EM_CLKH-EM_DIV) Input hold time, read data valid on D[31:0] after EM_CLK rising 1.9 ns (1) For more information about supported EMIF frequency, see Table 2-1. Table 4-6. 100-MHz EMIF SDRAM Interface Switching Characteristics(1) NO. PARAMETER MIN MAX UNIT 1 tc(EM_CLK) Cycle time, EMIF clock EM_CLK 10 ns 2 tw(EM_CLK) Pulse width, EMIF clock EM_CLK high or low 3 ns 3 td(EM_CLKH-EM_CSV)S Delay time, EM_CLK rising to EM_CS[0] valid 7.7 ns 4 toh(EM_CLKH-EM_CSIV)S Output hold time, EM_CLK rising to EM_CS[0] invalid 1.15 ns 5 td(EM_CLKH-EM_WE-DQMV)S Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid 7.7 ns 6 toh(EM_CLKH-EM_WE-DQMIV)S Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid 1.15 ns 7 td(EM_CLKH-EM_AV)S Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid 7.7 ns Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] 8 toh(EM_CLKH-EM_AIV)S 1.15 ns invalid 9 td(EM_CLKH-EM_DV)S Delay time, EM_CLK rising to EM_D[31:0] valid 7.7 ns 10 toh(EM_CLKH-EM_DIV)S Output hold time, EM_CLK rising to EM_D[31:0] invalid 1.15 ns 11 td(EM_CLKH-EM_RASV)S Delay time, EM_CLK rising to EM_RAS valid 7.7 ns 12 toh(EM_CLKH-EM_RASIV)S Output hold time, EM_CLK rising to EM_RAS invalid 1.15 ns 13 td(EM_CLKH-EM_CASV)S Delay time, EM_CLK rising to EM_CAS valid 7.7 ns 14 toh(EM_CLKH-EM_CASIV)S Output hold time, EM_CLK rising to EM_CAS invalid 1.15 ns 15 td(EM_CLKH-EM_WEV)S Delay time, EM_CLK rising to EM_WE valid 7.7 ns 16 toh(EM_CLKH-EM_WEIV)S Output hold time, EM_CLK rising to EM_WE invalid 1.15 ns 17 tdis(EM_CLKH-EM_DHZ)S Delay time, EM_CLK rising to EM_D[31:0] 3-stated 7.7 ns 18 tena(EM_CLKH-EM_DLZ)S Output hold time, EM_CLK rising to EM_D[31:0] driving 1.15 ns (1) For more information about supported EMIF frequency, see Table 2-1. Submit Documentation Feedback Peripheral and Electrical Specifications 49 |
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