TMS320C6726BRFP300 datasheet(97/118 Pages) TI

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4.15.3 I2C Electrical Data/Timing

4.15.3.1 Inter-Integrated Circuit (I2C) Timing

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-36 and Table 4-37 assume testing over recommended operating conditions (see Figure 4-38 and

Figure 4-39).

Table 4-36. I2C Input Timing Requirements

NO.

MIN

MAX

UNIT

Standard Mode

tc(SCL)

Cycle time, I2Cx_SCL

µs

Fast Mode

2.5

Standard Mode

4.7

Setup time, I2Cx_SCL high before I2Cx_SDA

tsu(SCLH-SDAL)

µs

low

Fast Mode

0.6

Standard Mode

th(SCLL-SDAL)

Hold time, I2Cx_SCL low after I2Cx_SDA low

µs

Fast Mode

0.6

Standard Mode

4.7

tw(SCLL)

Pulse duration, I2Cx_SCL low

µs

Fast Mode

1.3

Standard Mode

tw(SCLH)

Pulse duration, I2Cx_SCL high

µs

Fast Mode

0.6

Standard Mode

250

tsu(SDA-SCLH)

Setup time, I2Cx_SDA before I2Cx_SCL high

Fast Mode

100

Standard Mode

th(SDA-SCLL)

Hold time, I2Cx_SDA after I2Cx_SCL low

µs

Fast Mode

0.9

Standard Mode

4.7

tw(SDAH)

Pulse duration, I2Cx_SDA high

µs

Fast Mode

1.3

Standard Mode

1000

tr(SDA)

Rise time, I2Cx_SDA

Fast Mode

20 + 0.1Cb

300

Standard Mode

1000

tr(SCL)

Rise time, I2Cx_SCL

Fast Mode

20 + 0.1Cb

300

Standard Mode

300

tf(SDA)

Fall time, I2Cx_SDA

Fast Mode

20 + 0.1Cb

300

Standard Mode

300

tf(SCL)

Fall time, I2Cx_SCL

Fast Mode

20 + 0.1Cb

300

Standard Mode

Setup time, I2Cx_SCL high before I2Cx_SDA

tsu(SCLH-SDAH)

µs

high

Fast Mode

0.6

Standard Mode

N/A

tw(SP)

Pulse duration, spike (must be suppressed)

Fast Mode

Standard Mode

400

Capacitive load for each bus line

Fast Mode

400

Table 4-37. I2C Switching Characteristics(1)

NO.

PARAMETER

MIN

MAX

UNIT

Standard Mode

tc(SCL)

Cycle time, I2Cx_SCL

µs

Fast Mode

2.5

Standard Mode

4.7

Setup time, I2Cx_SCL high before I2Cx_SDA

tsu(SCLH-SDAL)

µs

low

Fast Mode

0.6

Standard Mode

th(SDAL-SCLL)

Hold time, I2Cx_SCL low after I2Cx_SDA low

µs

Fast Mode

0.6

(1)

I2C must be configured correctly to meet the timings in Table 4-37.

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