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CS495313 数据表(PDF) 25 Page - Cirrus Logic

部件名 CS495313
功能描述  Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology
PDF  36 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS495313 数据表(HTML) 25 Page - Cirrus Logic

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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705PP6
Copyright 2009 Cirrus Logic
25
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.19 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
(SD_CLKOUT = SD_CLKIN)
Parameter
Symbol
Min
Typical
Max
Unit
SD_CLKIN high time
tsdclkh
2.3
-
ns
SD_CLKIN low time
tsdclkl
2.3
-
ns
SD_CLKOUT rise/fall time
tsdclkrf
-1
ns
SD_CLKOUT Frequency
150
MHz
SD_CLKOUT duty cycle
-45
55
%
SD_CLKOUT rising edge to signal valid
tsdcmdv
-3.8
ns
Signal hold from SD_CLKOUT rising edge
tsdcmdh
1.1
-
ns
SD_CLKOUT rising edge to SD_DQMn valid
tsddqv
-3.8
-
ns
SD_DQMn hold from SD_CLKOUT rising edge
tsddqh
1.38
-
ns
SD_DATA valid setup to SD_CLKIN rising edge
tsddsu
1.3
-
ns
SD_DATA valid hold to SD_CLKIN rising edge
tsddh
1.38
-
ns
SD_CLKOUT rising edge to ADDRn valid
tsdav
-3.8
-
ns
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
tdaosstlr
tdaosclk
DAO_SCLK
DAO_LRCLK
tdaoslrts
tdaosdv
tdaosclk
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK



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