Pad

Zeros

MSB

1

2

3

5

4

6

10

11

12

1

MSB−1 MSB−2 MSB−3 MSB−4 MSB−5

MSB−8 MSB−9 LSB+1

LSB

16

8

7

9

MSB−6 MSB−7

Low Level

MSB

D6

D5

D4

D3

D2

D1

D0

D7

D7

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Access Cycle

Sample Cycle

Channel

Address

A/D Conversion Interval

Output Data

Format

Previous Conversion Data

Initialize

CS

I/O

CLOCK

DATA

OUT

DATA IN

EOC

INT

Initialize

DATA OUT

1

2

3

5

4

6

10

11

12

1

I/O CLOCK

MSB−1 MSB−2 MSB−3 MSB−4 MSB−5

MSB−8 MSB−9 LSB+1

LSB

Hi−Z State

DATA IN

8

7

9

MSB−6 MSB−7

D7

MSB

MSB

16

EOC

Initialize

Initialize

Shift in New Multiplexer Address, Simultaneously

Shift Out Previous Conversion Result

Access Cycle

Sample Cycle

CS

Previous Conversion Data

Pad Zeros

Channel

Address

Output Data

Format

A/D Conversion Interval

DATA IN Can be Tied or Held High

TLV2556-EP

PARAMETER MEASUREMENT INFORMATION (continued)

A.

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 51. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First

A.

To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 52. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, External Reference, Pin 19 =

EOC, Input = AIN0)

Copyright © 2008–2009, Texas Instruments Incorporated

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