GTL2003_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 27 July 2007

3 of 19

NXP Semiconductors

GTL2003

8-bit bidirectional low voltage translator

6.

Pinning information

6.1 Pinning

6.2 Pin description

[1]

DHVQFN package die supply ground is connected to both GND pin and exposed center pad. GND pin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

printed-circuit board in the thermal pad region.

Fig 2.

Pin configuration for TSSOP20

Fig 3.

Pin configuration for DHVQFN20

GTL2003PW

GND

GREF

SREF

DREF

S1

D1

S2

D2

S3

D3

S4

D4

S5

D5

S6

D6

S7

D7

S8

D8

002aac639

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

002aac640

GTL2003BQ

Transparent top view

D7

S6

S7

D6

S5

D5

S4

D4

S3

D3

S2

D2

S1

D1

SREF

DREF

9

12

8

13

7

14

6

15

5

16

4

17

3

18

2

19

terminal 1

index area

Table 3.

Pin description

Symbol

Pin

Description

GND

1[1]

ground (0 V)

SREF

2

source of reference transistor

S1 to S8

3, 4, 5, 6, 7, 8, 9, 10

Port S1 to Port S8

D1 to D8

18, 17, 16, 15, 14, 13, 12, 11

Port D1 to Port D8

DREF

19

drain of reference transistor

GREF

20

gate of reference transistor