LPC2124FBD64SLASH01 datasheet(17/40 Pages) NXP

17 / 40 page

LPC2114_2124_6

Product data sheet

Rev. 06 — 10 December 2007

17 of 40

NXP Semiconductors

LPC2114/2124

Single-chip 16/32-bit microcontrollers

6.12 SSP controller (LPC2114/2124/01 only)

Remark: This peripheral is available in LPC2114/2124/01 only.

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. The application can switch on

the ﬂy from SPI1 to SSP and back.

6.12.1 Features

• Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four to 16 bits per frame.

6.13 General purpose timers

The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally

generate interrupts or perform other actions at speciﬁed timer values, based on four

match registers. It also includes four capture inputs to trap the timer value when an input

signal transitions, optionally generating an interrupt. Multiple pins can be selected to

perform a single capture or match function, providing an application with ‘or’ and ‘and’, as

well as ‘broadcast’ functions among them.

6.13.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Four external outputs per timer corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

LPC2124FBD64/01 数据表(PDF) 17 Page - NXP Semiconductors

LPC2124FBD64/01 数据表(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载