LPC2124FBD64SLASH01 datasheet(27/40 Pages) NXP

27 / 40 page

LPC2114_2124_6

Product data sheet

Rev. 06 — 10 December 2007

27 of 40

NXP Semiconductors

LPC2114/2124

Single-chip 16/32-bit microcontrollers

[1]

Conditions: VSSA =0V, VDDA = 3.3 V.

[2]

The ADC is monotonic, there are no missing codes.

[3]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7]

The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

Table 7.

ADC static characteristics

VDDA = 2.5 V to 3.6 V unless otherwise speciﬁed; Tamb = −40 °C to +85 °C unless otherwise speciﬁed. ADC frequency

4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIA

analog input voltage

VDDA

Cia

analog input

capacitance

--1

differential linearity

error

[1][2][3] --

±1

LSB

EL(adj)

integral non-linearity

[1][4] --

±2

LSB

offset error

[1][5] --

±3

LSB

gain error

[1][6] --

±0.5

absolute error

[1][7] --

±4

LSB

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