P89LPC9211FDH datasheet(45/74 Pages) NXP

45 / 74 page

P89LPC92X1_1

Preliminary data sheet

Rev. 01 — 16 April 2009

45 of 74

NXP Semiconductors

P89LPC9201/9211/922A1/9241/9251

8-bit microcontroller with 8-bit ADC

7.28.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC9201/9211/922A1/9241/9251 through a two-wire serial interface. The NXP ICP

facility has made in-circuit programming in an embedded application - using commercially

available programmers - possible with a minimum of additional expense in components

and circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to

be available to interface your application to a commercial programmer in order to use this

feature. Additional details may be found in the

P89LPC9201/9211/922A1/9241/9251 User

manual.

7.28.7 IAP

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The NXP IAP has made in-application programming in an embedded application possible

without additional components. Two methods are available to accomplish IAP. A set of

predeﬁned IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of ﬂash sectors, pages, security

bits, conﬁguration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conﬂicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the

P89LPC9201/9211/922A1/9241/9251 User manual.

7.28.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC9201/9211/922A1/9241/9251 through the

serial port. This ﬁrmware is provided by NXP and embedded within each

P89LPC9201/9211/922A1/9241/9251 device. The NXP ISP facility has made in-system

programming in an embedded application possible with a minimum of additional expense

in components and circuit board area. The ISP function uses ﬁve pins (VDD, VSS, TXD,

RXD, and RST). Only a small connector needs to be available to interface your application

to an external circuit in order to use this feature.

7.28.9 Power-on reset code execution

The P89LPC9201/9211/922A1/9241/9251 contains two special ﬂash elements: the Boot

Vector and the Boot Status bit. Following reset, the P89LPC9201/9211/922A1/9241/9251

examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up

execution starts at location 0000H, which is the normal start address of the user’s

application code. When the Boot Status bit is set to a value other than zero, the contents

of the Boot Vector are used as the high byte of the execution address and the low byte is

set to 00H.

P89LPC9211FDH 数据表(PDF) 45 Page - NXP Semiconductors

P89LPC9211FDH 数据表(HTML) 45 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载