PCA9633_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 25 July 2008

29 of 43

NXP Semiconductors

PCA9633

[1]

[2]

Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.

13. Dynamic characteristics

[1]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2]

[3]

[4]

Address inputs

LOW-level input voltage

−0.5

-

HIGH-level input voltage

-

5.5

V

input leakage current

−1-

+1

µA

input capacitance

-

3.7

5

pF

Table 20.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 21.

Dynamic characteristics

Symbol Parameter

Conditions

Standard- mode

Fast-mode

Fast-mode

Unit

Min

Max

Min

Max

Min

Max

SCL clock frequency

[1]

0

100

0

400

0

1000

kHz

bus free time between a

STOP and START condition

4.7

-

1.3

-

0.5

-

µs

hold time (repeated) START

condition

4.0

-

0.6

-

0.26

-

µs

set-up time for a repeated

START condition

4.7

-

0.6

-

0.26

-

µs

set-up time for STOP

condition

4.0

-

0.6

-

0.26

-

µs

data hold time

0

-

0

-

0

-

ns

data valid acknowledge time

[2]

0.3

3.45

0.1

0.9

0.05

0.45

µs

data valid time

[3]

0.3

3.45

0.1

0.9

0.05

0.45

µs

data set-up time

250

-

100

-

50

-

ns

LOW period of the SCL

clock

4.7

-

1.3

-

0.5

-

µs

HIGH period of the SCL

clock

4.0

-

0.6

-

0.26

-

µs

fall time of both SDA and

SCL signals

[5][6]

-

300

-

120

ns

rise time of both SDA and

SCL signals

-

1000

-

120

ns

pulse width of spikes that

must be suppressed by the

input filter

[7]

-

50

-

50

-

50

ns