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PCF8566P 数据表(PDF) 21 Page - NXP Semiconductors

部件名 PCF8566P
功能描述  Universal LCD driver for low multiplex rates
PDF  48 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8566P 数据表(HTML) 21 Page - NXP Semiconductors

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PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
21 of 48
NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
8.1.1.1
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 13.
8.1.2 System configuration
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure 14.
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. (See
Figure 15).
Acknowledgement on the I2C-bus is illustrated in
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
Fig 13. Definition of START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig 14. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER



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