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PCF85133U/2DA/1 数据表(PDF) 30 Page - NXP Semiconductors

部件名 PCF85133U/2DA/1
功能描述  Universal LCD driver for low multiplex rates
PDF  41 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF85133U/2DA/1 数据表(HTML) 30 Page - NXP Semiconductors

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PCF85133_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 1 — 17 February 2009
30 of 41
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF85133 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be restored by the first PCF85133 to
assert SYNC. The timing relationships between the backplane waveforms and the SYNC
signal for the various drive modes of the PCF85133 are shown in Figure 21.
The contact resistance between the SYNC bumps of cascaded devices must be
controlled. If the resistance is too high then the device will not be able to synchronize
properly. This is particularly applicable to COG applications. Table 19 shows the limiting
values for contact resistance.
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 20. Cascaded PCF85133 configuration
Table 19.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000
Ω
3 to 5
2200
Ω
6 to 10
1200
Ω
11 to 16
700
Ω
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
80 segment drives
4 backplanes
80 segment drives
LCD PANEL
(up to 5120
elements)
PCF85133
(1)
A0
A1
A2
SA0
VSS
VSS
VSS
VDD
VDD
VLCD
VLCD
VDD
VLCD
001aaj581
SDA
SDAACK
SDAACK
SCL
SYNC
CLK
OSC
FF
FF
BP0 to BP3
(open-circuit)
A0
A1
A2
SA0
PCF85133
(2)
BP0 to BP3
R
tr
2Cb
≤



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