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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000016

VDIP1 Vinculum VNC1L Module Datasheet Version 1.01

Clearance No.: FTDI# 131

3.7.1 Timing Diagram – Parallel FIFO Read Transaction

When in parallel FIFO interface mode, the timing of a read is shown in Figure 3.6 and Table 3.9

Figure 3.6 - FIFO Read Cycle.

Time

Description

Min

Max

Unit

T1

RD# Active Pulse Width

50

-

ns

T2

RD# to RD# Pre-Charge Time

50 + T6

-

ns

T3

RD# Active to Valid Data*

20

50

ns

T4

Valid Data Hold Time from RD#

Inactive*

0

-

ns

T5

RD# Inactive to RXF#

0

25

ns

T6

RXF# Inactive After RD# Cycle

80

-

ns

Table 3.9 FIFO Read Cycle Timing

* Load = 30pF