ADT7420UCPZ-R2 datasheet(4/24 Pages) AD

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ADT7420

Preliminary Technical Data

Rev. PrA | Page 4 of 4

I2C TIMING SPECIFICATIONS

TA = −40°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns

(10% to 90% of VDD) and timed from a voltage level of 1.6 V.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SERIAL INTERFACE1, 2

See Figure 2

SCL Frequency

400

kHz

SCL High Pulse Width, t

HIGH

0.6

µs

SCL Low Pulse Width, t

LOW

1.3

µs

SCL, SDA Rise Time, t

0.3

µs

SCL, SDA Fall Time, t

0.3

µs

Hold Time (Start Condition), t

HD:STA

0.6

µs

After this period, the first clock is generated

Setup Time (Start Condition), t

SU:STA

0.6

µs

Relevant for repeated start condition

Data Setup Time, t

SU:DAT

0.25

µs

DD ≥ 3.0 V

0.35

µs

DD < 3.0 V

Setup Time (Stop Condition), t

SU:STO

0.6

µs

Data Hold Time, t

HD:DAT (Master)

µs

Bus-Free Time (Between Stop and Start Condition), t

BUF

1.3

µs

1 Sample tested during initial release to ensure compliance.

2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

Timing Diagram

tLOW

tHD:STA

tHD:DAT

tSU:DAT

tSU:STA

tHD:STA

tSU:STO

tHIGH

SCL

SDA

tBUF

Figure 2. Serial Interface Timing Diagram

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