SC18IM700IPW datasheet(13/22 Pages) NXP

13 / 22 page

SC18IM700_2

Product data sheet

Rev. 02 — 10 August 2007

13 of 22

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

Remark: The numbers used in the formulas are in decimal, but the numbers to program

I2CClkH and I2CClkL are in hex.

9.2.6 I2C-bus time-out (I2CTO)

The time-out register is used to determine the maximum time that SCL is allowed to be

LOW before the I2C-bus state machine is reset.

When the I2C-bus interface is running, I2CTO is loaded after each I2C-bus state transition.

The least signiﬁcant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1

will enable the time-out function. The time-out period can be calculated as follows:

The time-out value may vary, and it is an approximate value.

9.2.7 I2C-bus status register (I2CStat)

This register reports the I2C-bus transmit and receive frame status, whether the frame

transmits correctly or not.

Table 7.

I2C-bus clock frequency

I2CClk

(I2CClkH + I2CClkL)

I2C-bus clock frequency

10 (minimum)

369 kHz

246 kHz

147 kHz

123 kHz

74 kHz

61 kHz

100

37 kHz

Table 8.

I2CTO - I2C-bus time-out register (address 0x09h) bit description

Bit

Symbol

Description

7:1

TO[7:1]

time-out value

enable/disable time-out function

logic 0 = disable

logic 1 = enable

time-out period

I 2CTO 7:1

[] 256

57600

-----------------------------------------------

onds

sec

Table 9.

I2C-bus status

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C-bus status description

11110000

I2C_OK

11110001

I2C_NACK_ON_ADDRESS

11110010

I2C_NACK_ON_DATA

11111000

I2C_TIME_OUT

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