PIC18F23K20-ESLASHML datasheet(89/456 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41303G-page 89

PIC18F2XK20/4XK20

6.0

FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed one byte at

a time. A write to program memory is executed on

blocks of 64, 32 or 16 bytes at a time, depending on the

specific device (See Table 6-1). Program memory is

erased in blocks of 64 bytes at a time. The difference

between the write and erase block sizes requires from

1 to 4 block writes to restore the contents of a single

block erase. A bulk erase operation cannot be issued

from user code.

TABLE 6-1:

WRITE/ERASE BLOCK SIZES

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP

6.1

Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

The table read operation retrieves one byte of data

directly from program memory and places it into the

TABLAT register. Figure 6-1 shows the operation of a

table read.

The table write operation stores one byte of data from the

TABLAT register into a write block holding register. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 6.5 “Writing

to Flash Program Memory”. Figure 6-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. Tables contain-

ing data, rather than program instructions, are not

required to be word aligned. Therefore, a table can start

and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word aligned.

FIGURE 6-1:

TABLE READ OPERATION

Device

Write Block

Size (bytes)

Erase Block

Size (bytes)

PIC18F43K20,

PIC18F23K20

PIC18F24K20,

PIC18F25K20,

PIC18F44K20,

PIC18F45K20

PIC18F26K20,

PIC18F46K20

Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH

TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note

1: Table Pointer register points to a byte in program memory.

Program Memory

(TBLPTR)

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