Block Guide — S12BDM V4

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4.11 Instruction Tagging

The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace

history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the

CPU at a specific instruction. This is because execution already has begun by the time an operation is

visible outside the system. A separate instruction tagging mechanism is provided for this purpose.

The tag follows program information as it advances through the instruction queue. When a tagged

instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction.

NOTE:

Tagging is disabled when BDM becomes active and BDM serial commands are not

processed while tagging is active.

Executing the BDM TAGGO command configures two system pins for tagging. The TAGLO signal

shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal.

Table 4-3 shows the functions of the two tagging pins. The pins operate independently, that is the state

of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall

of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. Low

tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and

emulation expanded narrow mode).

4.12 Serial Communication Time-out

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If

BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command

was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the

SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any

time-out limit.

Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as

a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge

marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock

cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting

memory or the operating mode of the MCU. This is referred to as a soft-reset.

Table 4-3 Tag Pin Function

TAGHI

TAGLO

Tag

1

1

No tag

1

0

Low byte

0

1

High byte

0

0

Both bytes