Block Guide — S12BDM V4

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4.5 BDM Command Structure

Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a

16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte

or word implication in the command name.

NOTE:

8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If

reading an even address, the valid data will appear in the MSB. If reading an odd

address, the valid data will appear in the LSB.

NOTE:

16-bit misaligned reads and writes are not allowed. If attempted, the BDM will

ignore the least significant bit of the address and will assume an even address from

the remaining bits.

For hardware data read commands, the external host must wait 150 bus clock cycles after sending the

address before attempting to obtain the read data. This is to be certain that valid data is available in the

BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait

150 bus clock cycles after sending the data to be written before attempting to send a new command. This

is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle

delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a

free cycle before stealing a cycle.

For firmware read commands, the external host should wait 44 bus clock cycles after sending the

command opcode and before attempting to obtain the read data. This includes the potential of an extra 7

cycles when the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2, or 3 cycles),

(7 cycles could be needed if both occur). The 44 cycle wait allows enough time for the requested data to

be made available in the BDM shift register, ready to be shifted out.

NOTE:

This timing has increased from previous BDM modules due to the new capability in

which the BDM serial interface can potentially run faster than the bus. On previous

BDM modules this extra time could be hidden within the serial time.

For firmware write commands, the external host must wait 32 bus clock cycles after sending the data to be

written before attempting to send a new command. This is to avoid disturbing the BDM shift register

before the write has been completed.

The external host should wait 64 bus clock cycles after a TRACE1 or GO command before starting any

new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup

table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely

affect the exit from the standard BDM firmware lookup table.

NOTE:

If the bus rate of the target processor is unknown or could be changing, it is

recommended that the ACK (acknowledge function) be used to indicate when an

operation is complete. When using ACK, the delay times are automated.