PIC18F4580-ESLASHML datasheet(9/490 Pages) MICROCHIP

9 / 490 page

DS39637D-page 9

PIC18F2480/2580/4480/4580

1.0

DEVICE OVERVIEW

This document contains device specific information for

the following devices:

• PIC18F2480

• PIC18F2580

• PIC18F4480

• PIC18F4580

This family of devices offers the advantages of all

PIC18 microcontrollers – namely, high computational

performance at an economical price – with the addition

high-endurance,

Enhanced

Flash

program

memory. In

addition

these

features,

the

PIC18F2480/2580/4480/4580 family introduces design

enhancements that make these microcontrollers a

logical

choice

for

many

high-performance,

power-sensitive applications.

1.1

New Core Features

1.1.1

nanoWatt TECHNOLOGY

All of the devices in the PIC18F2480/2580/4480/4580

family incorporate a range of features that can signifi-

cantly reduce power consumption during operation.

Key items include:

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

• On-the-Fly Mode Switching: The

power-managed modes are invoked by user code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

• Lower Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer have been reduced by up to

80%, with typical values of 1.1 and 2.1

μA,

respectively.

• Extended Instruction Set: In addition to the

standard 75 instructions of the PIC18 instruction

set, PIC18F2480/2580/4480/4580 devices also

provide an optional extension to the core CPU

functionality. The added features include eight

additional instructions that augment indirect and

indexed addressing operations and the

implementation of Indexed Literal Offset

Addressing mode for many of the standard PIC18

instructions.

1.1.2

MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F2480/2580/4480/4580

family offer ten different oscillator options, allowing

users a wide range of choices in developing application

hardware. These include:

• Four Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same

pin options as the External Clock modes

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC

source (approximately 31 kHz, stable over

temperature and VDD), as well as a range of

6 user-selectable clock frequencies, between

125 kHz to 4 MHz, for a total of 8 clock

frequencies. This option frees the two oscillator

pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and

internal oscillator modes, which allows clock

speeds of up to 40 MHz. Used with the internal

oscillator, the PLL gives users a complete

selection of clock speeds, from 31 kHz to

32 MHz – all without using an external crystal or

clock circuit.

Besides its availability as a clock source, the internal

oscillator block provides a stable reference source that

gives the family additional features for robust

operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer-

ence signal provided by the internal oscillator. If a

clock failure occurs, the controller is switched to

the internal oscillator block, allowing for continued

low-speed operation or a safe application

shutdown.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

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