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PIC18F4580-E/ML 数据表(PDF) 13 Page - Microchip Technology |
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PIC18F4580-E/ML 数据表(HTML) 13 Page - Microchip Technology |
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13 / 490 page  © 2009 Microchip Technology Inc. DS39637D-page 13 PIC18F2480/2580/4480/4580 FIGURE 1-2: PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM Instruction Decode & Control Data Address<12> 12 Access BSR 44 PCH PCL PCLATH 8 31 Level Stack Program Counter PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> Address Latch Program Memory (16/32 Kbytes) Data Latch 20 8 8 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 3 ROM Latch PORTD RD0/PSP0 PCLATU PCU PORTE MCLR/VPP/RE3(1) RE2/CS/AN7/C2OUT RE0/RD/AN5 RE1/WR/AN6/C1OUT Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 3.0 “Oscillator Configurations” for additional information. /C1IN+ EUSART Comparator MSSP 10-Bit ADC Timer2 Timer1 Timer3 Timer0 CCP1 HLVD ECCP1 BOR Data EEPROM W Instruction Bus <16> STKPTR Bank 8 State Machine Control Signals 8 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer OSC1(2) OSC2(2) VDD, Brown-out Reset Internal Oscillator Fail-Safe Clock Monitor Reference Band Gap VSS MCLR(1) Block INTRC Oscillator 8 MHz Oscillator Single-Supply Programming In-Circuit Debugger T1OSI T1OSO RD1/PSP1/C1IN- RD2/PSP2/C2IN+ RD3/PSP3/C2IN- PORTA PORTB PORTC RA4/T0CKI RA5/AN4/SS/HLVDIN RB0/INT0/FLT0/AN10 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0/CVREF RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX OSC2/CLKO/RA6 RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD OSC1/CLKI/RA7 ECAN FSR0 FSR1 FSR2 inc/dec Address 12 Decode logic Data Latch Data Memory (.7, 1.5 Kbytes) Address Latch RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D |
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