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PCM4104IPFBREP 数据表(PDF) 21 Page - Texas Instruments |
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PCM4104IPFBREP 数据表(HTML) 21 Page - Texas Instruments |
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21 / 43 page ![]() www.ti.com LRCK BCK (BCKE = 0) DATA0 DATA1 t DS t DH t BKLRD BCK (BCKE = 1) t LRBKD t BCKP t BCKHL P A R A M E TE R D E S C R IP T IO N M IN M A X U N ITS 70 ns 30 ns 10 ns 10 ns 10 ns 10 ns 50 % BCK Cycle Time BCK High/Low Time LRCK Edge to BCK Sampling Edge Delay BCK Sampling Edge to LRCK Edge Delay Data Setup Time Data Hold Time LRCK Duty Cycle tBCKP tBCKHL tLRBKD tBKLRD tDS t DH − PCM4104-EP SBAS419 – JUNE 2007 Figure 11. Audio Serial Port Timing for Left Justified, Right Justified, and I2S Data Formats 21 Submit Documentation Feedback |
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