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MPC8308CVMADDA 数据表(PDF) 12 Page - Freescale Semiconductor, Inc |
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MPC8308CVMADDA 数据表(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 88 page  MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1 12 Freescale Semiconductor DDR2 SDRAM Figure 4 illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter. Figure 4. Timing Diagram for tDISKEW 6.2.2 DDR2 SDRAM Output AC Timing Specifications Table 18. DDR2 SDRAM Output AC Timing Specifications Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 7.5 10 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 266 MHz 2.9 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 266 MHz 2.33 — MCS[n] output setup with respect to MCK tDDKHCS ns 3 266 MHz 3.15 — MCS[n] output hold with respect to MCK tDDKHCX ns 3 266 MHz 3.15 — MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4 MDQ//MDM/MECC output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5 266 MHz 900 — MDQ//MDM/MECC output hold with respect to MDQS tDDKHDX, tDDKLDX ps 5 266 MHz 1100 — MCK[n] MCK[n] tMCK MDQ[x]/ MDQS[n] tDISKEW D1 D0 tDISKEW MECC[x] |
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