ADT7485AARMZ-R7 datasheet(4/12 Pages) ONSEMI

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ADT7485A

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ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.

Parameter

Unit

Max

Typ

Min

Test Conditions/Comments

Digital I/O (SST Pin)

High Impedance State Leakage, ILEAK

Device powered on SST bus;

VSST = 1.1 V, VCC = 3.3 V

±1.0

High Impedance State Leakage, ILEAK

Device non−powered on SST bus;

VSST = 1.1 V, VCC = 0 V

±10

Signal Noise Immunity, VNOISE

Noise glitches from 10 MHz to 100 MHz;

width up to 50 ns

300

p−p

SST Timing

Bitwise Period, tBIT

0.495

500

High Level Time for Logic 1, tH1

(Note 2)

tBIT defined in speed negotiation

0.6 x

tBIT

0.75 x

tBIT

0.8 x

tBIT

High Level Time for Logic 0, tH0

(Note 2)

0.2 x

tBIT

0.25 x

tBIT

0.4 x

tBIT

Time to Assert SST High for Logic 1,

tSU, HIGH

0.2 x

tBIT

Hold Time, tHOLD (Note 3)

See SST Specification Rev 1.0

0.5 x

tBIT−M

Stop Time, tSTOP

Device responding to a constant low level

driven by originator

1.25 x

tBIT

2 x tBIT

Time to Respond After a Reset, tRESET

0.4

Response Time to Speed Negotiation

After Powerup

Time after powerup when device can participate

in speed negotiation

500

1. Guaranteed by design, not production tested.

2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.

3. Device is compatible with hold time specification as driven by SST originator.

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