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ST72F324J2T6 数据表(PDF) 29 Page - STMicroelectronics |
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ST72F324J2T6 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 164 page ![]() ST72324Jx ST72324Kx 29/164 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Low Power Modes 6.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupt causes the device to exit from Wait mode. HALT The CRSR register is frozen. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 1 |
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