P912XDP512F0MPVR datasheet(325/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

325

7.3.2.9

Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)

Read or write: Anytime

All bits reset to zero.

76543210

EDG7B

EDG7A

EDG6B

EDG6A

EDG5B

EDG5A

EDG4B

EDG4A

Reset

00000000

Figure 7-13. Timer Control Register 3 (TCTL3)

76543210

EDG3B

EDG3A

EDG2B

EDG2A

EDG1B

EDG1A

EDG0B

EDG0A

Reset

00000000

Figure 7-14. Timer Control Register 4 (TCTL4)

Table 7-11. TCTL3/TCTL4 Field Descriptions

Field

Description

EDG[7:0]B

7, 5, 3, 1

Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector

circuits for each input capture channel. The four pairs of control bits in TCTL4 also conﬁgure the input capture

edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the

active edge for the 16-bit pulse accumulator PACB. See Table 7-12.

EDG[7:0]A

6, 4, 2, 0

Table 7-12. Edge Detector Circuit Conﬁguration

EDGxB

EDGxA

Conﬁguration

Capture disabled

Capture on rising edges only

Capture on falling edges only

Capture on any edge (rising or falling)

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