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P912XDP512F0MPVR 数据表(PDF) 326 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 326 Page - Freescale Semiconductor, Inc |
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326 / 1348 page ![]() Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.21 326 Freescale Semiconductor 7.3.2.10 Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register. 76543210 R C7I C6I C5I C4I C3I C2I C1I C0I W Reset 00000000 Figure 7-15. Timer Interrupt Enable Register (TIE) Table 7-13. TIE Field Descriptions Field Description 7:0 C[7:0]I Input Capture/Output Compare “x” Interrupt Enable 0 The corresponding flag is disabled from causing a hardware interrupt. 1 The corresponding flag is enabled to cause an interrupt. |
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