P912XDP512F0MPVR datasheet(567/1348 Pages) FREESCALE

部件名	P912XDP512F0MPVR

功能描述	HCS12X Microcontrollers

PDF	1348 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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567 / 1348 page

Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

567

14.4.10.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID.An

interrupt, indicated by ﬂag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the Reduced Power Mode, the LVIF is not cleared by the

VREG_3V3.

14.4.10.2 Autonomous Periodical Interrupt (API)

As soon as the conﬁgured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1.

Autonomous periodical interrupt (API)

APIE = 1

Table 14-10. Interrupt Vectors

Interrupt Source

Local Enable

P912XDP512F0MPVR 数据表(PDF) 567 Page - Freescale Semiconductor, Inc