P912XDP512F0MPVR datasheet(642/1348 Pages) FREESCALE

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Chapter 17 Memory Mapping Control (S12XMMCV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

642

Freescale Semiconductor

17.4.4

Chip Bus Control

The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and

XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus

swapping operations. All internal and external resources are connected to speciﬁc target buses (see

Figure 1-26).

Figure 17-26. S12X Architecture

17.4.4.1

Master Bus Prioritization

The following rules apply when prioritizing accesses over master buses:

•

The CPU has priority over the BDM, unless the BDM access is stalled for more than 128 cycles.

In the later case the CPU will be stalled after ﬁnishing the current operation and the BDM will gain

access to the bus.

•

XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU

and BDM for its duration.

XBus2

CPU

XFLASH

XEEPROM

IPBI

EBI

XBus0

ROM/REG

BDM

XBus1

RAM

XRAM

2 Kbyte Registers

S12X

XGATE

MMC

BDM

XGATE

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