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P912XDP512F0MPVR 数据表(PDF) 645 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 645 Page - Freescale Semiconductor, Inc |
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645 / 1348 page  Chapter 17 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 645 Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. A summary of PRR accesses is the following: • An aligned word access to a PRR will take 2 bus cycles. • A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the misaligned word access is not a PRR, the access will take only 3 cycles. • A byte access to a PRR will take 2 cycles. Table 17-22. PRR Listing PRR Name PRR Local Address PRR Location PORTA $0000 PIM PORTB $0001 PIM DDRA $0002 PIM DDRB $0003 PIM PORTC $0004 PIM PORTD $0005 PIM DDRC $0006 PIM DDRD $0007 PIM PORTE $0008 PIM DDRE $0009 PIM MMCCTL0 $000A MMC MODE $000B MMC PUCR $000C PIM RDRIV $000D PIM EBICTL0 $000E EBI EBICTL1 $000F EBI Reserved $0012 MMC MMCCTL1 $0013 MMC ECLKCTL $001C PIM Reserved $001D PIM PORTK $0032 PIM DDRK $0033 PIM |
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