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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

763

20.3.2.8.1

Debug Comparator Control Register (DBGXCTL)

The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in

the 8-byte window of the DBG module register address map.

Read: Anytime

Write: Anytime when S12XDBG not armed.

Address: 0x0028

76543210

NDB

TAG

BRK

RWE

SRC

COMPE

Reset

00000000

= Unimplemented or Reserved

Figure 20-13. Debug Comparator Control Register (Comparators A and C)

Address: 0x0028

76543210

SZE

TAG

BRK

RWE

SRC

COMPE

Reset

00000000

Figure 20-14. Debug Comparator Control Register (Comparators B and D)

Table 20-27. DBGXCTL Field Descriptions

Field

Description

SZE

(Comparators

B nd D)

Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the

associated comparator. This bit is ignored if the TAG bit in the same register is set.

0 Word/Byte access size is not used in comparison

1 Word/Byte access size is used in comparison

NDB

(Comparators

A and C

Not Data Bus Compare — The NDB bit controls whether the match occurs when the data bus matches the

comparator register value or when the data bus differs from the register value. Furthermore data bus bits can

be individually masked using the comparator data mask registers. This bit is only available for comparators

A and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality

for comparators B and D.

0 Match on data bus equivalence to comparator register contents

1 Match on data bus difference to comparator register contents

(Comparators

B and D)

Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the

associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.

This bit position has NDB functionality for comparators A and C

0 Word access size will be compared

1 Byte access size will be compared

TAG

Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the

matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.

0 Trigger immediately on match

1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated

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